[akd4371-b] 2007/07 - 1 - general description the akd4371 is an evaluation board for 24bit da c with headphone amplifier, AK4371. the akd4371 has the interface with akm?s adc evaluation boards. therefore, it?s easy to evaluate the AK4371. the adk4370 also has the digital audio in terface and can achieve the interface with digital audio systems via opt-connector. ordering guide akd4371-b --- evaluation board for AK4371 (cable for connecting with printer port of ib m-at compatible pc and control software are packed with this. this control software does not operate on windows nt.) function ? compatible with 2 types of interface - direct interface with akm?s a/d converter evaluation boards - on-board ak4116 as dir which accepts optical input ? 10pin header for serial control interface ? mini-jack for external stereo speaker ? on-board class-d speaker amplifier (ak7832) gnd ak4116 ( dir ) opt in (port1) dsp 10pin header (port2) AK4371 lout regulator vcc (5.0v) (3.3v) ak7832 (spk-amp) rout hpl hpr control data 10pin header (port3) hp sppr l/rout sppl rin1 rin3 rin2 lin2 lin3 mout lin1 figure 1. akd4371 block diagram * circuit diagram and pcb layout are attached at the end of this manual. a k4371 evaluation board rev.1 a kd4371-b
[akd4371-b] 2007/07 - 2 - evaluation board manual operation sequence 1) set up the power supply lines. [vcc] (red) = 5.0v : for regulator [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. 3.3v is supplied to AK4371 via the regulator. 2) set up the evaluation mode, jumper pins. (see the followings.) 3) power on. the AK4371 and ak4116 should be resets once bringing sw1(dac/dir_pdn) ?l? upon power-up. and the ak7832 should be resets once bringing sw2(spk_pdn) ?l? upon power-up. evaluation mode when evaluating the AK4371 using the port1(ak4116), it is possible to use the initial setting of the audio interface format (24bit msb justified). the ak4116 operates at fs of 32khz or more. if the fs is slower than 32khz, any other evaluation mode should be used. when inputting the data from the port2, the AK4371? s audio interface format should be set to correspond the input data?s audio interface fo rmat. refer to the AK4371?s datasheet. applicable evaluation mode (1) pll master mode (2) pll slave mode (2-1) pll reference clock : mcki pin (2-2) pll reference clock : bick or lrck pin (3) external slave mode (3-1) evaluation using dir (opt ical link) of ak4116 (3-2) evaluation connecting akd4371 with external dsp (4) external master mode
[akd4371-b] 2007/07 - 3 - (1) pll master mode port2 (dsp) is used. nothing should be connected to port1(dir). bick and lrck are supplied from port2.it is possible to evalua te at various sampling frequencie s using built-in the AK4371?s pll. a k4371 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 27mhz,26mhz,19.8mhz,19.68mhz, 19.2mhz,15.36mhz,14.4mhz,13mhz, 12mhz,11.2896mhz mclk figure 2. pll master mode the system clock should be connected to mclk of port2. sdti of port2 should be connected to sdto of dsp. the jp3(lrck2) and jp4(bick2)?s right side should be connected to lrck and bick of dsp. in case of supplying mcko to dsp, the test pin(mcko) should be connected to mclk of dsp. set up the jumper pins. jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8
[akd4371-b] 2007/07 - 4 - (2) pll slave mode (2-1) pll reference clock : mcki pin a k4371 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs ~ 64fs 256fs/128fs/64fs/32fs 27mhz,26mhz,19.8mhz,19.68mhz, 19.2mhz,15.36mhz,14.4mhz,13mhz, 12mhz,11.2896mhz mclk figure 3. pll master mode (pll reference clock : mcki pin) port2 (dsp) is used. nothing should be connected to port1(dir). mcko is needed for a synchronous signal of bick and lrck. mclk,bick,lrck and sdata are supplied from port2. the test pin(mcko) should be connected to mclk of dsp. set up the jumper pins. jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8
[akd4371-b] 2007/07 - 5 - (2-2) pll reference clock : bick or lrck pin AK4371 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs or 64fs figure 4. pll master mode (pll reference clock : bick or lrck pin) port2 (dsp) is used. nothing should be connected to port1(dir). bick,lrck and sdata are supplied from port2. set up the jumper pins. jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8
[akd4371-b] 2007/07 - 6 - (3) external slave mode the AK4371?s register should be set to ext slave mode. mcki frequency should be set to the same as the specification of dsp or dir. about the AK4371?s register definitions, refer to datasheet of the AK4371. AK4371 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs ~ 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 5. external slave mode (3-1) evaluation using dir (opt ical link) of ak4116 port1 (dir) is used. nothing should be connected to port2(dsp). set up the jumper pins. (3-2) evaluation connecting akd4371 with external dsp port2 (dsp) is used. nothing should be connected to port1(dir). set up the jumper pins. jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8 jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8
[akd4371-b] 2007/07 - 7 - (4) external master mode the AK4371?s register should be set to ext master mode . mcki frequency should be set to the same as dsp?s specification. about the AK4371?s register definitions, refer to datasheet of the AK4371. a k4371 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs, 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 6. ext master mode port2 (dsp) is used. nothing should be connected to port1 (dir). the system clock should be connected to mclk of port2. sdti of port2 should be connected to sdto of dsp. the jp4(lrck2) and jp3(bick2)?s right side should be connected to lrck and bick of dsp. set up the jumper pins. jp4 bick2 jp3 lrck2 jp6 bick jp7 lrck mclk jp5 sdto jp8
[akd4371-b] 2007/07 - 8 - other jumper pins set up jp1 (gnd) : analog ground and digital ground. open : separated. short : common. jp11 (inln) : setting of ak7832 input pin ?inln?. open : when sw2 (spk_pdn) is ?l?. short : when sw2 (spk_pdn) is ?h?. jp12 (inrn) : setting of ak7832 input pin ?inrn?. open : when sw2 (spk_pdn) is ?l?. short : when sw2 (spk_pdn) is ?h?. jp13 (dvdd_reg) : setting of power supply ?dvdd?. open : it supplies ?dvdd? from the outside. short : it supplies ?dvdd? fro m the regulator (3.3v). the function of the toggle sw upper-side is ?h? and lower-side is ?l?. [sw1] (dac/dir_pdn): power down of AK4371 and ak4116. keep ?h? during normal operation. [sw2] (spk_pdn): power down of ak7832. keep ?h? during normal operation. indication for led [led1] (erf): monitor int0 pin of the ak4116. led turns on when some error has occurred to ak4116.
[akd4371-b] 2007/07 - 9 - serial control the AK4371 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 (up -if) with pc by 10 wire flat cable packed with the akd4371. 10pin header csn 10 wire flat cable cclk cdti 10pin connector pc connect a kd4371 figure 7. connect of 10 wire flat cable (1) 3-wire serial control mode the jumper pins should be set to the followings. (2) i 2 c-bus control mode the jumper pins should be set to the followings. (2-1) in case of using cad0=0 (device address bits). (2-2) in case of using cad0=1 (device address bits). jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0 jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0 jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0
[akd4371-b] 2007/07 - 10 - input / output circuit (1) input circuit lin1/rin1, lin2/rin2, lin3/rin3 input circuits + c20 1u + c19 1u 6 4 3 j3 lin2/rin2 + c27 1u + c21 1u 6 4 3 j5 lin3/rin3 + c31 1u + c29 1u lin3 rin3 lin2 rin2 lin1 rin1 6 4 3 j2 lin1/rin1 figure 8. lin1/rin1,lin2/rin2,lin3/rin3 input circuits (2) output circuit 1) hpl/hpr output circuit + c25 100u 6 4 3 j4 hp + c28 100u r9 (short) hpr hpl r10(short) figure 9. hpl/hpr output circuit 2) mout output circuit 6 4 3 j1 mout + c18 1u mout figure 10. mout output circuit
[akd4371-b] 2007/07 - 11 - 3) lout/rout output circuit + c30 1u 6 4 3 j6 l/r out r12 47k r11 220 + c32 1u r14 47k r13 220 lout rout figure 11. lout/rout output circuit 4) speaker output circuit evaluation using ak7832?s speaker , the jumper pins should be set to the followings. 6 4 3 j8 spp_r 6 4 3 j7 spp_l vcrn vcrp vclp vcln 1 tp3 vclp 1 tp2 vcln 1 tp4 vcrn 1 tp5 vcrp figure 12. spk-amp output circuit ? akm assumes no responsibility for the trouble when using the above circuit examples. jp12 inrn jp11 inln
[akd4371-b] 2007/07 - 12 - control software manual set-up of evaluation board and control software 1. set up the akd4371 according to previous term. 2. connect ibm-at compatible pc with akd4371 by 10-lin e type flat cable (packed with akd4371). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?AK4371 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4371.exe? to set up the control program. 5. then please evaluate according to the follows. operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. 3. click ?write default? button explanation of each buttons 1. [port reset] : set up the usb interface board (akdusbif-a) when using the board. 2. [write default] : initialize the register of AK4371. 3. [all write] : write all registers that is currently displayed. 4. [function1] : dialog to write data by keyboard operation. 5. [function2] : dialog to write data by keyboard operation. 6. [function3] : the sequence of regist er setting can be set and executed. 7. [function4] : the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5] : the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save] : save the current register setting. 10. [open] : write the saved values to all register. 11. [write] : dialog to write data by mouse operation. indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
[akd4371-b] 2007/07 - 13 - explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the [write] button corresponding to each register to se t up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to AK4371, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to AK4371, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate datt there are dialogs corresponding to register of 05h , 06h , 09h , 0eh and 13h. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is wr itten to AK4371 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not re turn to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to AK4371, click [ok] button. if not, click [cancel] button.
[akd4371-b] 2007/07 - 14 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the AK4371. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.ak r) and click [open] button.
[akd4371-b] 2007/07 - 15 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. the default setting sequence dac->hp (3d=off) is displayed. jump to (3) below if the default setting sequence is used. go to (2) if the other setting sequence is required. (2) set the control sequence. set the address, data and interval time. set ?-1? to th e address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 13. window of [f3]
[akd4371-b] 2007/07 - 16 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be liste d up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 9 opens. figure 14. [f4] window
[akd4371-b] 2007/07 - 17 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the se quence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 10. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 15. [f4] window (2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [func tion4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
[akd4371-b] 2007/07 - 18 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 11 opens. figure 16. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 12. (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
[akd4371-b] 2007/07 - 19 - figure 17. [f5] window (2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displaye d on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register setting file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] bu tton on the main window, the re gister setting file (*.akr) should be loaded again in order to reflect the change.
[akd4371-b] 2007/07 - 20 - measurement results [measurement condition] ? measurement unit : audio precession system two cascade ? mclk : 11.2896mhz ? bick : 64fs ? fs : 44.1khz ? bit : 24bit ? measurement mode : ext slave mode ? power supply : avdd = hvdd = dvdd = pvdd = 3.3v ? measurement filter :22hz 20khz ? temperature : room parameter dac analog output characteristics result (lch / rch) unit dac -> hp amp (r l =16 ? ) thd+n (0dbfs output) 54.1 / 54.1 db d-range (-60db output, a-weighted) 92.7 / 92.7 db s/n (a-weighted) 93.0 / 93.0 db dac -> lout (r l =47k ? ) thd+n (0dbfs output) 59.8 / 60.0 db d-range (-60db output, a-weighted) 90.2 / 90.3 db s/n (a-weighted) 90.2 / 90.3 db
[akd4371-b] 2007/07 - 21 - [plot of headphone amp] akm hp-amp thd + n vs input level fs=44.1khz , fin=1khz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 18. thd+n vs. input level akm hp-amp thd + n vs input frequency fs=44.1khz , 0db input -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 19. thd+n vs. input frequency
[akd4371-b] 2007/07 - 22 - akm hp-amp linearity fs=44.1khz , fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 20. linearity akm hp-amp frequency response fs=44.1khz , 0db input -24 +2 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 -0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 21. frequency response (including external hpf)
[akd4371-b] 2007/07 - 23 - akm hp-amp fft fs=44.1khz , 0db input -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 22. fft plot(1khz,0db) akm hp-amp fft fs=44.1khz , -60db input -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 23. fft plot(1khz,-60db)
[akd4371-b] 2007/07 - 24 - akm hp-amp fft fs=44.1khz , no signal -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 24. fft plot(noise floor) akm hp-amp fft fs=44.1khz , outband noise -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz figure 25. out-band noise
[akd4371-b] 2007/07 - 25 - akm hp-amp crosstalk fs=44.1khz , 0db input -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 26. crosstalk
[akd4371-b] 2007/07 - 26 - revision history date (yy/mm/dd) manual revision board revision reason page contents 06/12/12 km086200 0 first edition change 27 c12 4.7nf 47nf 07/07/24 km086201 1 change device revision was changed. rev. a rev. b important notice these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a lin1 rin3 lin2 cclk csn hpr pdn lout rout dvdd hpl avdd_reg hvdd_reg mout rin2 rin1 lin3 mcki lrck bick sdata cdti d_reg vclp vcln vcrp vcrn spk_pdn avdd_reg title size document number rev date: sheet of AK4371 , ak7832 1 akd4371-b a3 13 friday, august 10, 2007 title size document number rev date: sheet of AK4371 , ak7832 1 akd4371-b a3 13 friday, august 10, 2007 title size document number rev date: sheet of AK4371 , ak7832 1 akd4371-b a3 13 friday, august 10, 2007 dgnd agnd ak7832 c17 0.1u c17 0.1u c11 0.1u c11 0.1u jp12 inrn jp12 inrn r4 51 r4 51 + c14 1u + c14 1u c5 0.1u c5 0.1u c9 0.1u c9 0.1u jp2 i2c_sel jp2 i2c_sel c16 0.01u c16 0.01u c3 0.1u c3 0.1u jp11 inln jp11 inln r3 51 r3 51 jp1 gnd jp1 gnd c12 47n c12 47n + c6 2.2u + c6 2.2u c7 0.22u c7 0.22u c1 0.1u c1 0.1u c13 0.1u c13 0.1u r2 51 r2 51 r6 10k r6 10k u1 AK4371vn u1 AK4371vn sdata 1 bick 2 lrck 3 mcki 4 dvdd 5 pvdd 6 vcoc 7 vss2 8 vss3 9 mcko 10 cdti/sda 11 csn/cad0 13 pdn 14 i2c 15 mutet 16 mout 17 lout 18 rout 19 vref 20 vcom 21 avdd 22 hvdd 23 hpl 26 rin2 27 lin2 28 rin3 29 lin3 30 rin1 31 lin1 32 cclk/scl 12 vss1 24 hpr 25 + c4 10u + c4 10u tp1 mcko tp1 mcko 1 + c8 10u + c8 10u r5 10 r5 10 c15 0.1u c15 0.1u + c10 10u + c10 10u u2 u2 pdn c3 sda c2 dvddi c1 vc b5 vss3 b4 inlp b3 inrp b2 scl b1 nc a5 inln a3 inrn a2 nc a1 nc e5 vclp e4 vss1 e3 vcrp e2 nc e1 vdd1 d5 vcln d4 vss2 d3 vcrn d2 vdd2 d1 vdd3 c5 i2cen c4 + c2 10u + c2 10u r1 51 r1 51 r7 51 r7 51 r8 47k r8 47k
a a b b c c d d e e e e d d c c b b a a vcc +5v vcrn vcrp vcln vclp lin3 rin3 lin2 rin2 lin1 rin1 mout hpr hpl lout rout dir_reg d_reg avdd_reg hvdd_reg dvdd title size document number rev date: sheet of input/output 1 akd4371-b a3 23 friday, august 10, 2007 title size document number rev date: sheet of input/output 1 akd4371-b a3 23 friday, august 10, 2007 title size document number rev date: sheet of input/output 1 akd4371-b a3 23 friday, august 10, 2007 l4 (short) l4 (short) 1 2 t1 ta48m33f t1 ta48m33f in out gnd r13 220 r13 220 + c30 1u + c30 1u j5 lin3/rin3 j5 lin3/rin3 6 4 3 + c18 1u + c18 1u l1 10u l1 10u 1 2 r9 (short) r9 (short) + c20 1u + c20 1u j6 l/r out j6 l/r out 6 4 3 + c22 47u + c22 47u tp5 vcrp tp5 vcrp 1 r11 220 r11 220 + c25 100u + c25 100u tp2 vcln tp2 vcln 1 + c27 1u + c27 1u j8 spp_r j8 spp_r 6 4 3 r12 47k r12 47k + c26 47u + c26 47u c23 0.1u c23 0.1u j2 lin1/rin1 j2 lin1/rin1 6 4 3 + c19 1u + c19 1u + c31 1u + c31 1u r10(short) r10(short) tp3 vclp tp3 vclp 1 j1 mout j1 mout 6 4 3 j3 lin2/rin2 j3 lin2/rin2 6 4 3 + c21 1u + c21 1u + c32 1u + c32 1u tp4 vcrn tp4 vcrn 1 + c29 1u + c29 1u c24 0.1u c24 0.1u l2 (short) l2 (short) 1 2 j4 hp j4 hp 6 4 3 l3 (short) l3 (short) 1 2 r14 47k r14 47k j7 spp_l j7 spp_l 6 4 3 + c28 100u + c28 100u jp13 dvdd_reg jp13 dvdd_reg
a a b b c c d d e e e e d d c c b b a a gnd gnd dir_reg csn cclk cdti cdto d_reg d_reg dir_reg cdti cclk csn mcki sdata lrck bick pdn d_reg cdto d_reg spk_pdn pdn d_reg dvdd title size document number rev date: sheet of clock 1 akd4371-b a2 33 friday, august 10, 2007 title size document number rev date: sheet of clock 1 akd4371-b a2 33 friday, august 10, 2007 title size document number rev date: sheet of clock 1 akd4371-b a2 33 friday, august 10, 2007 up-i/f csn scl/cclk sda/cdti sdti mclk lrck bick cdto lh lh r21 10k r21 10k u3 74hc14 u3 74hc14 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 vcc 14 gnd 7 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 c41 0.1u c41 0.1u jp10 cad0 jp10 cad0 x1 11.2896mhz x1 11.2896mhz 1 2 sw2 spk_pdn sw2 spk_pdn 2 1 3 r19 12k r19 12k r20 5.1 r20 5.1 d2 hsu119 d2 hsu119 k a r26 470 r26 470 r15 1k r15 1k port1 torx141 port1 torx141 out 1 vcc 3 gnd 2 r24 470 r24 470 c44 0.1u c44 0.1u u5 74avc8t245 u5 74avc8t245 a1 3 a2 4 a4 6 a5 7 a6 8 a7 9 a8 10 oe 22 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 vccb 24 gnd 13 a3 5 dir 2 vccb 23 vcca 1 gnd 11 gnd 12 c34 0.1u c34 0.1u c43 10p c43 10p r23 10k r23 10k l5 47u l5 47u 1 2 port3 port3 1 2 3 4 5 6 7 8 9 10 + c40 10u + c40 10u jp7 lrck jp7 lrck led1 erf led1 erf k a r25 10k r25 10k r18 470 r18 470 r16 10k r16 10k c39 0.1u c39 0.1u d1 hsu119 d1 hsu119 k a c37 0.1u c37 0.1u sw1 dac/dir_pdn sw1 dac/dir_pdn 2 1 3 u4 ak4116 u4 ak4116 rx0 1 dvdd 2 dvss 3 xti 4 xto 5 lrck 6 bick 7 sdto 8 daux 9 mcko 10 cdto 11 cdti 12 cclk 13 csn 14 int1 15 int0 16 pdn 17 avss 18 r 19 avdd 20 c33 0.1u c33 0.1u tp6 xti tp6 xti 1 c38 0.1u c38 0.1u + c36 10u + c36 10u c45 0.1u c45 0.1u jp4 bick2 jp4 bick2 port2 dsp port2 dsp 1 2 3 4 5 6 7 8 9 10 r22 470 r22 470 jp3 lrck2 jp3 lrck2 r27 10k r27 10k jp9 sda jp9 sda jp6 bick jp6 bick jp8 sdto jp8 sdto r17 10k r17 10k jp5 mclk jp5 mclk c35 0.1u c35 0.1u c42 10p c42 10p
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